H5PS5162FFR-Y5C 海力士Hynix 512Mb(32MX16)DDR2 SDRAM内存闪存flash
2021-08-07 02:17:10
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512Mb DDR2 SDRAM
H5PS5162FFR-xxC Series
H5PS5162FFR-xxL Series
H5PS5162FFR-xxI Series
Rev. 1.0 / July. 2008 2
H5PS5162FFR series
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
• VDD ,VDDQ =1.8 +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 3, 4, 5 and 6 supported
• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• Programmable burst length 4 / 8 with both nibble sequential and interleave mode
• Internal four bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 84ball FBGA(x16) : 8mm x 13mm
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Self-Refresh High Temperature Entry
• Partial Array Self Refresh support
H5PS5162FFR系列
1. 描述
1.1设备特性和订购信息
1.1.1关键特性
• VDD, vddq =1.8 +/- 0.1v
• 所有输入输出均兼容SSTL_18接口
• 全差分时钟输入(CK， /CK)操作
• 双数据速率接口
• 源同步数据事务与双向数据频闪对齐(DQS, DQS)
• 差分数据频闪仪(DQS, DQS)
• DQS上的数据输出，读取时DQS边(边DQ)
• 写入DQS中心时的数据输入(居中DQ)
• 芯片上DLL将DQ、DQS和DQS转换与CK转换对齐
• DM掩码在数据频闪的上升边和下降边写入数据
• 所有地址和控制输入，除了数据，数据频闪和数据掩码锁存在时钟上升边缘
• 可编程CAS延迟3,4,5和6的支持
• 可编程附加延迟0,1,2,3,4和5的支持
• 可编程突发长度4 / 8与咬顺序和交错模式
• 内部四个银行操作与单个脉冲RAS
• 支持自动刷新和自刷新
• 支持tRAS锁定
• 8K刷新周期/64ms
• JEDEC标准84球FBGA(x16): 8mm x 13mm
• 由EMRS控制的全强度驱动器选项
• 在Die终止支持
• 支持Off Chip Driver Impedance Adjustment
• 自刷新高温入口
• 部分数组自刷新支持
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